Տեղեկատվական տեխնոլոգիաների կրթական եւ հետազոտական կենտրոն
YSU Information Technologies Educational and Research Center
Established in 2007, IT Educational and Research Center (IT ERC) serves as an interdisciplinary hub for educational program. Headed by Prof. Samvel K. Shoukourian:
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Valery A. Vardanyan

Associate Professor | Chair of Information Systems

Latest Publications (87)
Testing electronic memories based on fault and test algorithm periodicity
2017 | Patent
SYNOPSYS, INC. (Mountain View, CA). 9831000. Nov 28, 2017
Vrezh Sargsyan, Valery A. Vardanian , Samvel K. Shoukourian , Yervant Zorian, Avetik Yessayan
An efficient approach for memory repair by reducing the number of spares
2015 | Article
East-West Design & Test Symposium (EWDTS) Batumi, Georgia September 26-29, 2015, pp. 21-25 (english)
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T. Grigoryan, H. Malkhasyan, G. Mushyan, V. Vardanian
Fault Collapsing For Digital Circuits Based On Relations Between Stuck-At Faults
2015 | Article
IEEE Proceedings "Computer Science and Informatio Technologies (CSIT)", USA, 2015, pp. 15-18 (English)
Extending fault periodicity table for testing faults in memories under 20nm
2014 | Article
East-West Design & Test Symposium (EWDTS), Kiev, Ukraine September 26-29, 2014, pp. 5 - 9 (english)
“An Efficient Fault Diagnosis and Localization Algorithm for Successive-Approximation Analog to Digital Converters''
2012 | Article
Proc. IEEE East-West Design and Test Symposium, Kharkov National University of Radioelectronics, Kharkov, Ukraine, Sep. 14-17, 2012, pp. 15-18
Alexanyan K., Amirkhanyan K., Karapetyan S., Shoukourian S. , Shubat A., Vardanian V. , Zorian Y.
“Various methods and apparatuses for memory modeling using a structural primitive verification for memory compilers”
2012 | Thesis
US Patent No. 8,112,730, 2012
“A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs”
2012 | Article
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Volume 31, Number 6, June 2012, pp. 941-949
"An Efficient Fault Diagnosis and Localization Algorithm for Successive-Approximation Analog to Digital Converters"
2012 | Article
IEEE East-West Design and Test Symposium (EWDTS), Ukraine, 2012, pp. 15-18
K. Amirkhanyan, A. Davtyan, G. Harutyunyan , T. Melkumyan, S. Shoukourian , V. Vardanian , Y. Zorian
"Application of Defect Injection Flow for Fault Validation in Memories"
2012 | Article
IEEE East-West Design and Test Symposium (EWDTS), Ukraine, 2012, pp. 19-22
Karen Amirkhanyan, Karen Darbinyan, Arman Davtyan, Gurgen Harutyunyan , Samvel Shoukourian , Valery Vardanian , Yervant Zorian
“GENERATION OF MEMORY STRUCTURAL MODEL BASED ON MEMORY LAYOUT”
2012 | Article
No. 13/531,189, Filing date – June 22, 2012
T. Melkumyan, V.A. Vardanian
“Histogram based ADC BIST”
2011 | Article
Proc. Int’l Conference on Computer Science and Information Technologies (CSIT’11), Yerevan, Armenia, 2011, pp. 300-303
Թեստային հարցերի և խնդիրների շտեմարան
2011 | Book
Երևան, Ճարտարագետ, 2011:—306 էջ
K. Aleksanyan, V. A. Vardanian , Y. Zorian
“Various methods and apparatuses for effective yield enhancement of good chip dies having memories per wafer”
2011 | Article
US Patent No. 7890900, USA, 2011
“Generic BIST Architecture for Testing of Content Addressable Memories”
2011 | Article
IEEE International On-Line Testing Symposium (IOLTS), Greece, 2011, pp. 86-91
“A Robust Solution for Embedded Memory Test and Repair”
2011 | Article
IEEE Asian Test Symposium (ATS), India, 2011, pp. 461-462
“Symmetry Measure for Memory Test and Its Application in BIST Optimization”
2011 | Article
Journal of Electronic Testing: Theory and Applications (JETTA), Volume 27, Number 6, December 2011, pp. 753-766
“TESTING ELECTRONIC MEMORIES BASED ON FAULT AND TEST ALGORITHM PERIODICITY”
2011 | Article
No. 13/183,468, Filing date - July 15, 2011
Karen Amirkhanyan, Hayk Grigoryan, Gurgen Harutyunyan , Tatevik Melkumyan, Samvel Shoukourian , Alex Shubat, Valery Vardanian , Yervant Zorian
“DETECTING RANDOM TELEGRAPH NOISE INDUCED FAILURES IN AN ELECTRONIC MEMORY”
2011 | Article
No. 13/183,471, Filing date - July 15, 2011
“DETERMINING A DESIRABLE NUMBER OF SEGMENTS FOR A MULTI-SEGMENT SINGLE ERROR CORRECTING CODING SCHEME”
2011 | Article
No. 13/310,479, Filing date – December 2, 2011
“Minimal Algorithms for Testing Content-Addressable Memories”
2010 | Thesis
In proc. of IEEE East-West Design & Test Symposium 2010, St. Petersburg, Russia, September 17-20, 2010
Aleksanyan K., Amirkhanyan K., Shoukourian S. , Vardanian V. , Zorian Y.
“Memory Modeling Using an Intermediate Level Structural Description”
2010 | Article
US Patent, No 7768840, USA, 2010
“Minimal March Test Algorithms for Detection of All Realistic Two-Operation, Two-Cell Dynamic Faults from Subclasses Sav and Sva”
2010 | Article
Reports of National Academy of Sciences of Armenia, 2010, Vol. 110, No. 2, pp. 143-150
Vardanyan V.A. , Bozoyan Sh.E., Simonyan S.H., Vardanyan R.R., Maranjyan H.B., Buniatyan V.V., Khudaverdyan S.Kh., Petrosyan S.G., Babayan A.H., Harutyunyan A.G., Travajyan M.G., Yeghiazaryan S.S., Gomtsyan H.A., Melikyan V.Sh., Movsisyan V.M., Muradyan M.A., Ayvazyan G.E., Melkonyan S.V., Minasyan A.K., Tumanyan A.K., Stepanyan H.L., Tananyan H.G.
I-IV Armenian Microelectronics Olympiad Tests and Problems
2009 | Book
SEUA, Yerevan, 2009.-218 P. (in Armenian)
H. Avetisyan, G. Harutyunyan , V.A. Vardanian , Y. Zorian
“An Efficient March Test for Detection of All Two-Operation Dynamic Faults from Subclass Sav”
2009 | Article
IEEE East-West Design and Test Symposium (EWDTS), Russia, 2009, pp. 175-178
“An Efficient March Test Algorithm for Detection of Resistive Shorts in Multi-Port SRAMs”
2009 | Article
Computer Science and Information Technologies (CSIT), Armenia, 2009, pp. 435-438
Vardanyan V.A. , Melikyan V.Sh., Movsisyan V.M., Bozoyan Sh.E., Simonyan S.H., Vardanyan R.R., Maranjyan H.B., Buniatyan V.V., Khudaverdyan S.Kh., Petrosyan S.G., Babayan A.H., Harutyunyan A.G., Travajyan M.G., Yeghiazaryan S.S., Gomtsyan H.A., Muradyan M.A., Ayvazyan G.E., Melkonyan S.V., Minasyan A.K., Tumanyan A.K., Stepanyan H.L.
I-III Armenian Microelectronics Olympiad Tests and Problems
2008 | Book
SEUA, Yerevan, 2008.-161 P. (in Armenian)
“An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories”
2008 | Article
IEEE VLSI Test Symposium (VTS), USA, 2008, pp. 95 – 100
G. Harutunyan , D. Melkumyan, H. Elchyan, V. Vardanian
“An Efficient Method for Generation of March Tests Based on Formulas”
2008 | Article
Mathematical problems of cybernetics and computer science, Armenia, 2008, pp. 5-17
“Efficient March-Like Algorithm for Detection of All Two-Operation Dynamic Faults from Subclass Sav”,
2008 | Article
Mathematical problems of cybernetics and computer science, Armenia, 2008, pp. 18-24
K. Aleksanyan, V.A. Vardanian
“Yield Improvement Based on Full Repair of SRAMs with Defective Redundancies”
2007 | Thesis
Proceedings of IEEE East-West Design & Test International Symposium, Yerevan, Armenia, 2007
T.A. Gjonjyan, J.T. Sargsyan, V. Vardanian
“Fast Generation of March Tests for Fault Detection and Diagnosis in Static Random Access Memories”
2007 | Thesis
Proceedings of IEEE East-West Design & Test International Symposium, Yerevan, Armenia, 2007
V.A. Vardanian , A. Yessayan
“Innovation and its Impact on the Solutions Proposed by Virage Logic”
2007 | Article
Proc. Armtech Congress’07, Armenian Technology Congress, San Francisco, 2007, 2 p
“Minimal March Tests for Detection of Dynamic Faults in Random Access Memories”
2007 | Article
Journal of Electronic Testing: Theory and Applications (JETTA), Volume 23, Number 1, February 2007, pp. 55-74
"A March-Based Fault Location Algorithm with Partial and Full Diagnosis for All Simple Static Faults in Random Access Memories”
2007 | Article
IEEE Design and Diagnosis of Electronic Circuits and Systems (DDECS), Poland, 2007, pp. 145-148
“Minimal March Tests for Dynamic Faults in Random Access Memories”
2007 | Article
IEEE European Test Symposium (ETS), Germany, 2007, pp. 223 – 227
“An Efficient 2-Phase March Algorithm for Full Diagnosis of All Simple Static Faults in Random Access Memories”
2007 | Article
IEEE East-West Design and Test Symposium (EWDTS), Armenia, 2007, pp. 110-113
T. Gyonjyan, V. A. Vardanian
“An Efficient Algorithm for Generating Minimal March Tests for Fault Detection and Diagnosis in Static Random Access Memories”
2006 | Thesis
International Design and Test Workshop, Dubai, November 19-20, 2006
Y. Zorian, G. Torjyan, A. Harutyunyan, V. Vardanian
Apparatus, method, and system to allocate redundant components with subsets of the redundant components
2006 | Article
US Patent, No. 7,149,921, USA, 2006
”Minimal March-Based Fault Location Algorithm with Partial Diagnosis for All Static Faults in Random Access Memories”
2006 | Article
IEEE Design and Diagnosis of Electronic Circuits and Systems (DDECS), Czech Republic, 2006, pp. 260-265
Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories”
2006 | Article
IEEE VLSI Test Symposium (VTS), USA, 2006, pp. 120-125
“Minimal March Tests for Dynamic Faults in Random Access Memories”
2006 | Article
IEEE European Test Symposium (ETS), UK, 2006, pp. 43-48
“A March Based Algorithm for Location and Full Diagnosis of All Unlinked Static Faults”
2006 | Article
IEEE Memory Technology, Design and Testing (MTDT), Taiwan, 2006, pp 9-14
“A March Test for Full Diagnosis of All Simple Static Faults in Random Access Memories”
2006 | Article
IEEE East-West Design and Test Workshop (EWDTW), Russia, 2006, pp. 68-71
L.B. Mirzoyan, V.A. Vardanian
“Design-for-Checkability methods for Improvement of the Error Detection Probability of Concurrent Checkers”
2005 | Article
Int. Conf. CSIT’05, Yerevan, 2005, pp. 515-518
K. Aleksanyan, V.A. Vardanian
“Yield Improvement for SRAMs Based on the Repair of Defective Redundancies”
2005 | Article
Int. Conf. CSIT’05, Yerevan, 2005, pp. 534-537
Y. Zorian, V.A. Vardanian , K. Aleksanyan, K. Amirkhanyan
“Impact of Soft Error Challenge on SoC Design”
2005 | Article
Proc. IEEE Int. On-Line Test Symposium, IOLTS05, Saint Raphael, France, pp. 63-68, 2005
K. Aleksanyan, V.A. Vardanian , Y. Zorian
“Yield Prediction and Evaluation for Embedded SRAM and Memory System Compilers”
2005 | Article
Digest of Papers, 10th IEEE European Test Symposium, Tallinn, Estonia, pp. 273-278, 2005
“Minimal March Tests for Unlinked Static Faults in Random Access Memories”
2005 | Article
IEEE VLSI Test Symposium (VTS), USA, 2005, pp. 53-59
Minimal March-Based Fault Location Algorithm with Partial Diagnosis for Random Access Memories”
2005 | Article
Computer Science and Information Technologies (CSIT), Armenia, 2005, pp. 519-522
N. Derhacobian, V.A. Vardanian , Y. Zorian
Embedded memory reliability: the SER challenge
2004 | Article
Records of IEEE Int. Workshop Memory Technology, Design and Testing, MTDT, San Jose, USA, 2004, pp. 104-110
SoC yield optimization via an embedded memory test and repair infrastructure
2004 | Article
IEEE Design & Test of Computers, vol.21, May-June, 2004, pp. 200-207
A methodology for design and evaluation of redundancy allocation algorithms
2004 | Article
Proc. IEEE VLSI Test Symposium, Napa Valley, USA, 2004, pp. 249-255
V. A. Vardanian , T. A. Gyonjyan
A New March-Based Fault Location Algorithm With Partial Diagnosis for Static Random Access Memories
2003 | Article
Proc. Int. Conf. CSIT’03, Yerevan, pp. 378-381, 2003
V. Vardanian , G. Gabrielyan
A Tool for Evaluation and Comparison of Redundancy Allocation Algorithms for Static Random Access Memories
2003 | Article
Proc. Int. Conf. CSIT’03, Yerevan, pp. 391-394, 2003
V. A. Vardanian , Y. Zorian
‘A March-based fault location algorithm for static random access memories’
2002 | Article
Records of IEEE Int. Workshop on Memory Technology, Design and Testing’, MTDT’02, Isle of Bendor, France, pp. 62-67, 2002
‘An approach for evaluation of redundancy analysis algorithms’
2001 | Article
Records of IEEE Int. Workshop on Memory Technology, Design and Testing’, MTDT’01, San Jose, USA, pp. 51-55, 2001
V. A. Vardanian , L.B. Mirzoyan
‘A method for improvement of the error detection ability of concurrent checkers’
2001 | Article
Proc. Int. Conf. CSIT’01, Yerevan, pp. 349-353, 2001
‘Improving the error detection ability of concurrent checkers by observation point insertion in the circuit under check’
2000 | Thesis
DATE 2000, Design, Automation and Test in Europe, Paris, p. 762, 2000
V. A. Vardanian , L.B. Mirzoyan
‘Increasing the error detection probability of concurrent checkers by observation point insertion in the circuit under check’
1999 | Article
Proc. Int. Conf. CSIT’99, Yerevan, pp. 371-375, 1999
‘Exact probabilistic analysis of error detection for parity checkers’
1997 | Article
In: “Investigation of Error Detection Probability and Latency of Parity Checking for a Circuit Under Check”, Final Report of On-Line Testing Group: Technical Report, System Test and Reliability Laboratory, American University of Armenia, Yerevan, pp. 8-31, 1997
‘Exact probabilistic analysis of error detection for modulo 3 checkers'
1997 | Article
Proceedings of International Conference on Computer Science and Information Technologies (CSIT’97), Yerevan, 1997, pp. 311-313
Exact probabilistic analysis of error detection for parity checkers’
1997 | Article
Proceedings of the 15th IEEE VLSI Test Symposium, Monterey (USA), IEEE CS Press, pp. 222-227, 1997
‘On the complexity of regularity tests for partially specified Boolean functions.’
1997 | Article
Transactions of the Institute for Informatics and Automation Problems of the National Academy of Sciences of the Republic of Armenia, vol. XVII, pp. 92-104, 1997
On completely robust path delay fault testable realization of logic functions’
1996 | Thesis
In Annual Report of System Test and Reliability Laboratory, American University of Armenia, Yerevan, 1996
“О реализации логических функций при помощи комбинационных схем, тестируемых по отношению к неисправностям задержек путей”
1996 | Article
Доклады Национальной Академии Наук Армении, т. 96, # 2-4, 1996, стр. 38-42
‘On completely robust path delay fault testable realization of logic functions.’
1996 | Article
Proceedings of the 14th IEEE VLSI Test Symposium, Princeton (USA), 1996, IEEE CS Press, pp. 302-307, 1996
'On the complexity of dynamic tests for logic functions'
1994 | Article
"Acta Cybernetica", Szeged (Hungary), vol 11, No. 4, pp. 333-343, 1994
'On the complexity of terminal stuck-at fault detection tests for monotone Boolean functions'
1994 | Article
Proceedings of the 12th IEEE VLSI Test Symposium, Cherry Hill (USA) 1994, IEEE CS Press, pp. 182-185, 1994
'On rank selection probabilities for almost all stack filters'
1994 | Article
"Advances in Modelling & Analysis" (France), B, vol. 31, No. 1, pp. 43-54, 1994
“О сложности полных проверяющих тестов для монотонных булевых функций”
1993 | Article
Доклады Национальной Академии Наук Армении, т. 94, # 2, 1993, стр. 93-97
'On the complexity of dynamic tests for logic functions'
1993 | Thesis
Preprint, Yerevan, Publishers of the Armenian National Academy of Sciences, 13 p., 1993
“Оценки пассивной сложности для булевых функций”
1990 | Thesis
Тезисы докладов 9-й Всесоюзной конференции по Проблемам теоретической кибернетики, Волгоград, Изд-во ВГУ, ч. 1, т. 1, стр. 23, 1990
“О сложности единичных и полных динамических тестов для функций к-значной логики”
1988 | Article
Тезисы докладов 8-й Всесоюзной конференции по Проблемам теоретической кибернетики, Горький, Изд-во ГГУ, ч. 1, стр. 60-61, 1988
“Автоматизированная система генерации функциональных тестов для устройств с микропрограммным управлением”
1988 | Article
Тезисы докладов Всесоюзной конференции по САПР СБИС, Ереван, Изд-во АН Арм. ССР, стр. 14-15, 1988
“О сложности динамических тестов для функций к-значной логики”
1988 | Article
“Кибернетика”, Киев, Изд-во “Наукова думка”, # 3, стр. 29-36, 1988
“Об одном методе синтеза легко тестируемых схем”
1987 | Article
Автоматика и телемеханика, Москва, Изд-во Наука, # 7, стр. 136-139, 1987
“О сложности единичных динамических тестов для монотонных булевых функций”
1987 | Article
“Кибернетика”, Киев, Изд-во “Наукова думка”, # 3, стр. 23-26, 1987
“Оценки сложности динамических тестов для функций к-значной логики”
1986 | Article
Тезисы докладов 4-й конференции молодых ученых Закавказских республик по Проблемам автоматического управления, Тбилиси, Изд-во “Мецниереба”, стр. 289-291, 1986
“Активности аргументов булевых функций и синтез легко тестируемых схем”
1986 | Thesis
Тезисы докладов 5-й Научно-технической конференции молодых ученых района им. 26 комиссаров г. Еревана, Ереван, Изд-во АН Арм. ССР, стр. 31, 1986.
“О сложности полных динамических тестов для монотонных булевых функций”
1986 | Thesis
Тезисы докладов 5-й Научно-технической конференции молодых ученых района им. 26 комиссаров г. Еревана, Ереван, Изд-во АН Арм. ССР, стр. 30, 1986
“О сложности динамических тестов для функций к-значной логики”
1986 | Article
В сборнике: “Теоретические проблемы кибернетики”, Саратов, Изд-во СГУ, ч. 1, стр. 40-41, 1986
“О сложности тестов активностей для частичных булевых функций”
1986 | Article
Автоматика и телемеханика, Москва, Изд-во Наука, # 7, стр. 118-124, 1986
“Оценки сложности динамических тестов для частичных булевых функций”
1985 | Article
Тезисы докладов 7-й Всесоюзной конференции по Проблемам теоретической кибернетики, Иркутск, Изд-во ИГУ, ч. 1, стр. 42-43, 1985
“Распознавание неисправностей комбинационных схем при помощи динамического тестирования”
1985 | Article
Тезисы докладов Всесоюзной конференции по Математическим методам распознавания образов, Ереван, Изд-во АН Арм. ССР, стр. 33-35, 1985
'On the length of single dynamic tests for monotone Boolean functions'
1985 | Article
In: Proc. 5th Int. Conference Fundamentals of Computation Theory, "Lecture Notes in Computer Science", Berlin etc: Springer-Verlag, vol. 199, pp. 442-449, 1985
“О сложности динамических тестов для монотонных булевых функций”
1985 | Article
Доклады Академии Наук Арм. ССР, т. 80, # 4, 1985, стр. 147-151
“О сложности динамических тестов для булевых функций”
1983 | Article
Доклады Академии Наук Арм. ССР, т. 77, # 3, 1983, стр. 113-116